Current applications (e.g., big-data analytics, in-memory databases and large-scale High Performance Computing (HPC) simulations) are driving high-performance system architectures to include both large amounts of memory and high memory bandwidths. Conventional approaches for increasing memory capacity include attaching a network of memory modules to each physical memory port on a processor. Conventional approaches for increasing available memory bandwidth include multi-channel (e.g., dual, triple and quad) memory architecture that increases the available number of mediums (e.g., wires) to communicate with memory (e.g., random access memory (RAM)).
Decisions of whether to use large amounts of memory or high memory bandwidths often exert contradictory or competing pressures on hardware design. Demands for higher-performance memories (larger memory bandwidth) typically lead to choices that reduce the amount of memory modules that can be accommodated in conventional systems. For example, while prior double data rate (DDR) (utilizing both the rising and falling edge of a system clock to potentially double the memory speed) standards have supported multiple dual in-line memory modules (DIMM)s per memory channel, DDR4 currently supports a single DIMM per channel to improve higher-frequency operation. Similarly, some conventional memory interfaces based on high-performance serial interfaces attach a single memory module directly to a memory channel port on a processor. Some conventional systems (e.g., Hybrid Memory Cube (HMC)) attempt to maintain large memory capacity by attaching a network of memory modules including a plurality of memory modules connected to the single memory module attached directly to the memory channel port on the processor.